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DS1339 Serial Real-Time Clock
PIN ASSIGNMENT (Top View)
X1 X2 VBACKUP GND VCC SQW/ INT SCL SDA
FEATURES
Real-time clock (RTC) counts seconds, minutes, hours, day, date, month, and year with leap-year compensation valid up to 2100 2-wire serial interface Two time-of-day alarms Programmable square-wave output Oscillator stop flag Automatic power-fail detect and switch circuitry Trickle charge capability
8-Pin mSOP
Package Dimension Information
http://www.maxim-ic.com/TechSupport/DallasPackInfo.htm
PIN DESCRIPTION
PART PINPACKAGE 8 SOP 8 SOP 8 SOP TOP MARK 1339 ##-2 1339 ##-3 1339 ##-33 VCC X1, X2 GND SDA SCL VBACKUP SQW/ INT - Power Supply - 32.768kHz Crystal Connection - Ground - Serial Data - Serial Clock - Secondary Power Supply - Square-Wave/Interrupt Output
ORDERING INFORMATION
DS1339U-2 DS1339U-3 DS1339U-33
## = second line, revision code 2 = 2.0V, VCC 10% 3 = 3.0V, VCC 10% 33 = 3.3V, VCC 10%
APPLICATIONS
Handhelds (GPS, POS Terminal) Consumer Electronics (Set-Top Box, Digital Recording, Network Appliance) Office Equipment (Fax/Printer, Copier) Medical (Glucometer, Medicine Dispenser) Telecommunications (Router, Switcher, Server) Other (Utility Meter, Vending Machine, Thermostat, Modem)
TYPICAL OPERATING CIRCUIT
VCC VCC CRYSTAL VCC RPU RPU 1 6 CPU 5 X1 SCL X2 2 8 VCC SQ W /INT 7
i
DS1339
SDA VBACKUP GND 4 3
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: http://www.maxim-ic.com/errata.
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072302
DS1339
DESCRIPTION
The DS1339 serial real-time clock is a low-power clock/date device with two programmable time-of-day alarms and a programmable square-wave output. Address and data are transferred serially by a 2-wire bidirectional bus. The clock/date provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM indicator. The DS1339 has a built-in power-sense circuit that detects power failures and automatically switches to the backup supply.
OPERATION
The DS1339 operates as a slave device on the serial bus. Access is obtained by implementing a START condition and providing a device identification code followed by data. Subsequent registers can be accessed sequentially until a STOP condition is executed. The device is fully accessible and data can be written and read when VCC is greater than VPF. However, when VCC falls below VPF, the internal clock registers are blocked from any access. If VPF is less than VBACKUP, the device power is switched from VCC to VBACKUP when VCC drops below VPF. If VPF is greater than VBACKUP, the device power is switched from VCC to VBACKUP when VCC drops below VBACKUP. The registers are maintained from the VBACKUP source until VCC is returned to nominal levels. The block diagram in Figure 1 shows the main elements of the serial real-time clock.
Figure 1. BLOCK DIAGRAM
X1 X2
TIMEKEEPING, CONTROL, AND TRICKLE CHARGE REGISTERS
OSCILLATOR AND DIVIDER
VCC VBACKUP
POWER CONTROL
CONTROL LOGIC
SQW/ INT
SCL SDA
SERIAL BUS INTERFACE
ADDRESS REGISTER
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SIGNAL DESCRIPTIONS
VCC, GND - DC power is provided to the device on these pins. SCL (Serial Clock Input) - SCL is used to synchronize data movement on the serial interface. SDA (Serial Data Input/Output) - SDA is the input/output pin for the 2-wire serial interface. The SDA pin is an open-drain output and requires an external pullup resistor. VBACKUP (Secondary Supply Input) - Connection for a secondary power supply. Supply voltage must be held between 1.3V and 3.7V for proper operation. This pin can be connected to a primary cell such as a lithium button cell. Additionally, this pin can be connected to a rechargeable cell or a super cap when used with the trickle charge feature. SQW/ INT (Square-Wave/Interrupt Output) - Programmable square-wave or interrupt-output signal. The SQW/ INT pin is an open-drain output and requires an external pullup resistor. X1, X2 - These signals are connections for a standard 32.768kHz quartz crystal. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 6pF. For more information about crystal selection and crystal layout considerations, refer to Application Note 58 "Crystal Considerations with Dallas Real-Time Clocks." The DS1339 can also be driven by an external 32.768kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated. The oscillator is controlled by an enable bit in the control register. Oscillator startup times are highly dependent upon crystal characteristics, PC board leakage, and layout. High ESR and excessive capacitive loads are the major contributors to long startup times. A circuit using a crystal with the recommended characteristics and proper layout usually starts within one second.
TYPICAL PC BOARD LAYOUT FOR CRYSTAL
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CLOCK ACCURACY
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error is added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit can result in the clock running fast. Refer to Application Note 58 "Crystal Considerations with Dallas Real-Time Clocks" for detailed information.
ADDRESS MAP
The address map for the registers of the DS1339 is shown in Figure 2. During a multibyte access, when the address pointer reaches the end of the register space (10h), it wraps around to location 00h. On a 2wire START, STOP, or address pointer incrementing to location 00h, the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock can continue to run. This eliminates the need to re-read the registers in case of an update of the main registers during a read.
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Figure 2. DS1339 TIMEKEEPER REGISTERS
ADDRESS 00H 01H BIT7 0 0 BIT6 BIT5 10 SECONDS 10 MINUTES AM/PM 02H 03H 04H 05H 06H 07H 08H A1M1 A1M2 0 0 0 CENTURY 12/24 10HR 0 0 0 10 YEAR 10 SECONDS 10 MINUTES AM/PM 09H A1M3 12/24 10HR 10HR HOUR 0 0 10 DATE 10 MO 0 0 DATE MONTH YEAR SECONDS MINUTES DAY Day Date Month/ Century Year Alarm 1 Seconds Alarm 1 Minutes Alarm 1 Hours Alarm 1 Day Alarm 1 Date Alarm 2 Minutes Alarm 2 Hours Alarm 2 Day Alarm 2 Date A1IE A1F ROUT0 Control Status Trickle Charge 10HR HOUR Hours BIT4 BIT3 BIT2 BIT1 BIT0 FUNCTION Seconds Minutes RANGE 00-59 00-59 1-12 + AM/PM 00-23 1-7 00-31 01-12 + Century 00-99 00-59 00-59 1-12 + AM/PM 00-23 DAY DATE 1-7 1-31 SECONDS MINUTES
0AH
A1M4
DY/DT
10 DATE
0BH
A2M2
10 MINUTES AM/PM
MINUTES
00-59 1-12 + AM/PM 00-23
0CH
A2M3
12/24 10HR
10HR
HOUR
0DH
A2M4
DY/DT
10 DATE
DAY DATE RS1 0 DS1 INTCN 0 DS0 A2IE A2F ROUT1
1-7 1-31 -- -- --
0EH 0FH 10H
EOSC
0 0 TCS2
BBSQI 0 TCS1
RS2 0 TCS0
OSF TCS3
Note: Unless otherwise specified, the registers' state are not defined when power is first applied or VCC and VBACKUP falls below the VBACKUP min.
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TIME AND DATE OPERATION
The time and date information is obtained by reading the appropriate register bytes. The real-time clock registers are illustrated in Figure 2. The time and date are set or initialized by writing the appropriate register bytes. The contents of the time and date registers are in the binary coded decimal (BCD) format. The DS1339 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12-hour or 24-hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20-23 hours). All hours values, including the alarms, must be re-entered whenever the 12/24-hour mode bit is changed. The century bit (bit 7 of the month register) is toggled when the years register overflows from 99 to 00. The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined, but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time and date entries result in undefined operation. When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. When reading the time and date registers, the user buffers are synchronized to the internal registers on any START or STOP, and when the address pointer rolls over to 0. The countdown chain is reset whenever the seconds register is written. Write transfers occur on the acknowledge pulse from the device. To avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be written within one second. The 1Hz square-wave output, if enabled, transitions high 500ms after the seconds data transfer, provided the oscillator is already running.
ALARMS
The DS1339 contains two time-of-day/date alarms. Alarm 1 can be set by writing to registers 07h to 0Ah. Alarm 2 can be set by writing to registers 0Bh to 0Dh. The alarms can be programmed (by the alarm enable and INTCN bits of the control register) to activate the SQW/ INT output on an alarm match condition. Bit 7 of each of the time-of-day/date alarm registers are mask bits (Figure 3). When all of the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping registers 00h-06h match the values stored in the time-of-day/date alarm registers. The alarms can also be programmed to repeat every second, minute, hour, day, or date. Figure 3 shows the possible settings. Configurations not listed in the table result in illogical operation. The DY/DT bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0 to 5 of that register reflects the day of the week or the date of the month. If DY/DT is written to a logic 0, the alarm is the result of a match with date of the month. If DY/DT is written to a logic 1, the alarm is the result of a match with day of the week. When the RTC register values match alarm register settings, the corresponding alarm flag (A1F or A2F) bit is set to logic 1. If the corresponding alarm interrupt enable (A1IE or A2IE) is also set to logic 1 and the INTCN bit is set to logic 1, the alarm condition activates the SQW/ INT signal.
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Figure 3. ALARM MASK BITS
DY/DT X X X X 0 1 ALARM 1 REGISTER MASK BITS (BIT 7) A1M4 A1M3 A1M2 A1M1 1 1 1 1 1 1 1 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ALARM RATE Alarm once per second Alarm when seconds match Alarm when minutes and seconds match Alarm when hours, minutes, and seconds match Alarm when date, hours, minutes, and seconds match Alarm when day, hours, minutes, and seconds match
DY/DT X X X 0 1
ALARM 2 REGISTER MASK BITS (BIT 7) A2M4 A2M3 A2M2 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0
ALARM RATE Alarm once per minute (00 second of every minute) Alarm when minutes match Alarm when hours and minutes match Alarm when date, hours, and minutes match Alarm when day, hours, and minutes match
SPECIAL PURPOSE REGISTERS
The DS1339 has two additional registers (control and status) that control the RTC, alarms, and squarewave output.
CONTROL REGISTER (0Eh)
Bit 7
EOSC
Bit 6
0
Bit 5
BBSQI
Bit 4
RS2
Bit 3
RS1
Bit 2
INTCN
Bit 1
A2IE
Bit 0
A1IE
EOSC (Enable Oscillator) - This bit when set to logic 0 starts the oscillator. When this bit is set to a
logic 1, the oscillator is stopped. This bit is enabled (logic 0) when power is first applied. BBSQI (Battery-Backed Square-Wave and Interrupt Enable) - This bit when set to a logic 1 enables the square-wave or interrupt output when VCC is absent and the DS1339 is being powered by the VBACKUP pin. When BBSQI is a logic 0, the SQW/ INT pin goes high impedance when VCC falls below the powerfail trip point. This bit is disabled (logic 0) when power is first applied. RS2 and RS1 (Rate Select) - These bits control the frequency of the square-wave output when the square wave has been enabled. Figure 4 shows the square-wave frequencies that can be selected with the RS bits. These bits are both set to logic 1 (32kHz) when power is first applied.
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Figure 4. SQUARE-WAVE OUTPUT FREQUENCY
RS2 0 0 1 1 RS1 0 1 0 1 SQUARE-WAVE OUTPUT FREQUENCY 1Hz 4.096kHz 8.192kHz 32.768kHz
INTCN (Interrupt Control) - This bit controls the relationship between the two alarms and the interrupt output pins. When the INTCN bit is set to logic 1, a match between the timekeeping registers and the Alarm 1 or Alarm 2 registers activate the SQW/ INT pin (provided that the alarms are enabled).When the INTCN bit is set to logic 0, a square wave is output on the SQW/ INT pin. This bit is set to logic 0 when power is first applied. A1IE (Alarm 1 Interrupt Enable) - When set to logic 1, this bit permits the A1F bit in the status register to assert SQW/ INT (when INTCN = 1). When the A1IE bit is set to logic 0 or INTCN is set to logic 0, the A1F bit does not initiate the an interrupt signal. The A1IE bit is disabled (logic 0) when power is first applied. A2IE (Alarm 2 Interrupt Enable) - When set to a logic 1, this bit permits the A2F bit in the status register to assert SQW/ INT (when INTCN = 1). When the A2IE bit is set to logic 0 or INTCN is set to logic 0, the A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first applied.
STATUS REGISTER (0Fh)
Bit 7 OSF Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 A2F Bit 0 A1F
OSF (Oscillator Stop Flag) - A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period of time and can be used to jud ge the validity of the clock and date data. This bit is edge-triggered and set to logic 1 anytime the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set: 1) 2) 3) 4) The first time power is applied. The voltage present on both VCC and VBACKUP are insufficient to support oscillation. The EOSC bit is turned off. External influences on the crystal (e.g., noise, leakage, etc.).
This bit remains at logic 1 until written to logic 0. This bit can only be written to a logic 0. Attempting to write to logic 1 leaves the value unchanged. A1F (Alarm 1 Flag) - A logic 1 in the A1F bit indicates that the time matched the Alarm 1 registers. If the A1IE bit is a logic 1 and the INTCN bit is set to a logic 1, the SQW/ INT pin is also be asserted. A1F
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is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged. A2F (Alarm 2 Flag) - A logic 1 in the A2F bit indicates that the time matched the Alarm 2 registers. If the A2IE bit is a logic 1 and the INTCN bit is set to a logic 1, the SQW/ INT pin is also asserted. A2F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
TRICKLE CHARGE REGISTER (10h)
The simplified schematic of Figure 6 shows the basic components of the trickle charger. The tricklecharge select (TCS) bits (bits 4-7) control the selection of the trickle charger. In order to prevent accidental enabling, only a pattern on 1010 enables the trickle charger. All other patterns disable the trickle charger. The trickle charger is disabled when power is first applied. The diode select (DS) bits (bits 2 and 3) select whether or not a diode is connected between VCC and VBACKUP. The ROUT bits (bits 0, 1) select the value of the resistor connected between VCC and VBACKUP. Bit values are shown in Figure 5.
Figure 5. TRICKLE CHARGE REGISTER (10h) BIT VALUES
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 TCS3 TCS2 TCS1 TCS0 DS1 DS0 X X X X 0 0 X X X X 1 1 X X X X X X 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 0 BIT 1 ROUT1 X X 0 0 0 1 1 1 1 BIT 0 ROUT0 X X 0 1 1 0 0 1 1 FUNCTION Disabled Disabled Disabled No diode, 250W resistor One diode, 250W resistor No diode, 2kW resistor One diode, 2kW resistor No diode, 4kW resistor One diode, 4kW resistor
The user determines diode and resistor selection according to the maximum current desired for battery or super cap charging. The maximum charging current can be calculated as illustrated in the following example: Assume that a system power supply of 3.3V is applied to VCC and a super cap is connected to VBACKUP. Also assume that the trickle charger has been enabled with a diode and resistor R2 between VCC and VBACKUP. The maximum current IMAX would, therefore, be calculated as follows: IMAX = (3.3V - diode drop) / R2 (3.3V - 0.7V) / 2kW 1.3mA As the super cap or battery charges, the voltage drop between VCC and VBACKUP decreases and, therefore, the charge current decreases.
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Figure 6. PROGRAMMABLE TRICKLE CHARGE
R1
VCC
250W R2 2kW R3 4kW
VBACKUP
1 OF 16 SELECT
NOTE: ONLY 1010 ENABLES CHARGER
1 OF 2 SELECT
1 OF 3 SELECT
TCS3
BIT 7
TCS2
BIT 6
TCS1
BIT 5
TCS0
BIT 4
DS1
BIT 3
DS0
BIT 2
ROUT1
BIT 1
ROUT0
BIT 0
TCS0-3 = TRICKLE CHARGE SELECT DS0-1 = DIODE SELECT ROUT0-1 = RESISTOR SELECT
TRICKLE CHARGE REGISTER
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DS1339
2-WIRE SERIAL DATA BUS
The DS1339 supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1339 operates as a slave on the 2-wire bus. Connections to the bus are made by the open-drain I/O lines SDA and SCL. The following bus protocol has been defined (Figure 7): Data transfer can be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH are interpreted as control signals.
Accordingly, the following bus conditions have been defined: Bus Not Busy: Both data and clock lines remain HIGH. Start Data Transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop Data Transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data Valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.
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Figure 7. DATA TRANSFER ON 2-WIRE SERIAL BUS
Depending upon the state of the R/ W bit, two types of data transfer are possible: 1) Data Transfer from a Master Transmitter to a Slave Receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data is transferred with the most significant bit (MSB) first. 2) Data Transfer from a Slave Transmitter to a Master Receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. This is followed by the slave transmitting a number of data bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a "not acknowledge" is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. Data is transferred with the MSB first.
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The DS1339 can operate in the following two modes: 1) Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. After each byte is received an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit (Figure 8). The slave address byte is the first byte received after the START condition is generated by the master. The slave address byte contains the 7-bit DS1339 address, which is 1101000, followed by the direction bit (R/ W ), which, for a write, is a 0. After receiving and decoding the slave address byte, the slave outputs an acknowledge on the SDA line. After the DS1339 acknowledges the slave address + write bit, the master transmits a register address to the DS1339. This sets the register pointer on the DS1339, with the DS1339 acknowledging the transfer. The master can then transmit zero or more bytes of data, with the DS1339 acknowledging each byte received. The address pointer increments after each byte is transferred. The master generates a STOP condition to terminate the data write. 2) Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS1339 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer (Figure 9). The slave address byte is the first byte received after the START condition is generated by the master. The slave address byte contains the 7-bit DS1339 address, which is 1101000, followed by the direction bit (R/ W ), which, for a read, is a 1. After receiving and decoding the slave address byte the slave outputs an acknowledge on the SDA line. The DS1339 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode, the first address that is read is the last one stored in the register pointer. The address pointer is incremented after each byte is transferred. The DS1339 must receive a "not acknowledge" to end a read.
Figure 8. DATA WRITE: SLAVE RECEIVER MODE
Figure 9. DATA READ: SLAVE TRANSMITTER MODE
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ABSOLUTE MAXIMUM RATINGS*
Voltage Range on Any Pin Relative to Ground Operating Temperature Range Storage Temperature Range Soldering Temperature Range -0.3V to +6.0V -40C to +85C -55C to +125C See IPC/JEDEC J-STD-020A
*This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Supply Voltage, DS1339-2 Supply Voltage, DS1339-3 Supply Voltage, DS1339-33 Backup Supply Voltage Logic 1 Logic 0 Power-Fail Voltage, DS1339-2 Power-Fail Voltage, DS1339-3 Power-Fail Voltage, DS1339-33 SYMBOL VCC VCC VCC VBACKUP VIH VIL VPF VPF VPF MIN 1.8 2.7 2.97 1.3 0.7 VCC -0.5 1.58 2.45 2.70
(TA = -40C to +85C) (Note 12) MAX UNITS 2.2 V 3.3 V 3.63 V 3.7 V VCC + 0.5 V 0.3 VCC V 1.80 V 2.70 V 2.97 V NOTES
TYP 2.0 3.0 3.3 3.0
1.70 2.59 2.85
DC ELECTRICAL CHARACTERISTICS
(VCC = MIN to MAX, TA = -40C to +85C) (Note 12) PARAMETER Input Leakage I/O Leakage Logic 0 Out VOL = 0.4V, VCC > VCC Min (-3, -33), VCC 2.0V (-2) Logic 0 Out VOL = 0.2 (VCC) 1.8V < VCC < 2.0V (DS1339-2) Logic 0 Out VOL - 0.2 (VCC) 1.3V < VCC < 1.8V (DS1339-2) VCC Active Current Vcc Standby Current Trickle Charge Resistor Register 10h = A5h, VCC = Typ, VBACKUP = 0V Trickle Charge Resistor Register 10h = A6h, VCC = Typ, VBACKUP = 0V Trickle Charge Resistor Register 10h = A7h, VCC = Typ, VBACKUP = 0V VBACKUP Leakage Current SYMBOL ILI ILO IOL IOL IOL ICCA ICCS R1 R2 R3 IBKLKG 80 250 2000 4000 25 100 MIN TYP MAX 1 1 3 3 250 450 150 UNITS mA mA mA mA A mA mA nA NOTES 1 2 2 2 2 3 4
DC ELECTRICAL CHARACTERISTICS
PARAMETER VBACKUP Current EOSC = 0, SQW Off VBACKUP Current EOSC = 0, SQW On VBACKUP Current EOSC = 1 SYMBOL IBKOSC IBKSQW IBKDR
(VCC = 0V, TA = -40C to +85C) (Note 12) MIN TYP 400 600 10 MAX 700 1000 100 UNITS nA nA nA NOTES 10 10 10
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CRYSTAL SPECIFICATIONS*
PARAMETER Nominal Frequency Series Resistance Load Capacitance SYMBOL FO ESR CL MIN TYP 32.768 6 MAX 45 UNITS kHz k pF NOTES
*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58 "Crystal Considerations for Dallas Real-Time Clocks" for additional specifications.
CHIP AND PACKAGE INFORMATION
TRANSISTOR COUNT: 10,950 PROCESS: CMOS THERMAL RESISTANCE, TYP, sop: qJA, +207C/W, qJC +40C/W
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AC ELECTRICAL CHARACTERISTICS
(VCC = MIN to MAX, TA = -40C to +85C) (Note 12) PARAMETER SCL Clock Frequency Bus Free Time Between a STOP and START Condition Hold Time (Repeated) START Condition LOW Period of SCL Clock HIGH Period of SCL Clock Setup Time for a Repeated START Condition Data Hold Time SYMBOL fSCL CONDITION Fast Mode Standard Mode Fast Mode tBUF Standard Mode Fast Mode tHD:STA Standard Mode Fast Mode Standard Mode Fast Mode Standard Mode Fast Mode tSU:STA Standard Mode Fast Mode Standard Mode Fast Mode Standard Mode Fast Mode tR Standard Mode Fast Mode tF Standard Mode Fast Mode Standard Mode 20 + 0.1CB 0.6 4.0 400 10 100
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MIN 100
TYP
MAX 400 100
UNITS kHz
NOTES
1.3 ms 4.7 0.6 4.0 1.3 4.7 0.6 4.0 0.6 4.7 0 0 100 250 300 20 + 0.1CB 1000 300 ns 8 0.9 ms ms 5
tLOW
ms ms
tHIGH
tHD:DAT
ms ns
6, 7
Data Setup Time Rise Time of Both SDA and SCL Signals Fall Time of Both SDA and SCL Signals Setup Time for STOP Condition Capacitive Load for Each Bus Line I/O Capacitance Oscillator Stop Flag (OSF) Delay
tSU:DAT
9
ns
8
tSU:STO CB CI/O tOSF
ms pF pF ms 11 8
DS1339
Figure 10. TIMING DIAGRAM
Figure 11. POWER-UP/DOWN TIMING
VCC V PF(max) VPF(min) t VCCF t VCCR tREC INPUTS
RECOGNIZED
DON'T CARE
RECOGNIZED
OUTPUTS
HIGH-Z VALID VALID
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POWER-UP DOWN CHARACTERISTICS
PARAMETER Recovery at Power-up VCC Fall Time; VPF(MAX) to VPF(MIN) VCC Rise Time; VPF(MIN) to VPF(MAX) SYMBOL tREC tVCCF tVCCR 300 0 MIN
(TA = -40C to +85C) (Note 12) TYP MAX 2 UNITS ms ms ms NOTES 13
Warning: Under no circumstances are negative undershoots, of any amplitude, allowed when the device is in backup-battery mode.
NOTES:
SCL only. SDA, and SQW/ INT . ICCA: SCL at fSC max, VIL = 0.0V, VIH = VCC, trickle charge disabled. Specified with 2-wire bus inactive, VIL = 0.0V, VIH = VCC, trickle charge disabled. After this period, the first clock pulse is generated. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. 7) The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. 8) CB: Total capacitance of one bus line in pF. 9) A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT to 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. 10) Using recommended crystal on X1 and X2. 11) The parameter tOSF is the period of time the oscillator must be stopped in order for the OSF flag to be set over the voltage range of 0V VCC VCCMAX and 1.3V VBACKUP 3.7V. 12) Limits at -40C are guaranteed by design and are not production tested. 13) This delay applies only if the oscillator is running. If the oscillator is disabled or stopped, no powerup delay occurs. 1) 2) 3) 4) 5) 6)
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